1. Field of the Invention
The present invention relates to a CMOS image sensor and a method for fabricating the same.
2. Description of the Related Art
Generally, an image sensor is a semiconductor device used to convert an optical image into an electrical signal. Image sensors may generally be classified as either charge-coupled devices (CCDs) or complementary metal oxide semiconductor (CMOS) image sensors (CISs).
A CCD has a plurality of photodiodes (PDs) arranged in matrix form for converting an optical signal into an electrical signal. A CCD includes a plurality of vertical charge coupled devices (VCCDs), a horizontal charge coupled device (HCCD), and a sense amplifier. The VCCDs are formed between respective PDs arranged in matrix form and transfers charges generated in each PD in a vertical direction. The HCCD transfers the charges transferred by each VCCD in a horizontal direction. The sense amplifier senses the horizontally transferred charges and generates an electrical signal therefrom.
CCDs are complex and have high power consumption. In addition, the fabrication process of CCDs is complex because the process requires a multi-step photo process. It is also difficult to decrease the size of CCDs because of the difficulty in integrating a controller, a signal processor, and an analog-to-digital (A/D) converter in a chip of the CCD.
Recently, effort has been directed to producing CISs that are capable of overcoming the defects of CCDs. A CIS is a device employing MOS transistors corresponding to the number of unit pixels formed in a semiconductor substrate using a CMOS fabrication technology. A CIS is capable of sequentially detecting, by the respective MOS transistors, an output from each unit pixel. In CMOS fabrication technology, a controller and a signal processor are used as peripheral circuits. More particularly, in a CIS, a photodiode and a MOS transistor are formed within a unit pixel. A CIS can thereby sequentially detect an electrical signal of each unit pixel in order to capture an image.
Using CMOS fabrication technology, a CIS has relatively low power consumption and a relatively simple fabrication process in part because of the decreased number of photo process steps. Further, due in part to the integration of a controller, a signal processor, an A/D converter, and the like into a CIS chip, it is less difficult to decrease the size of a CIS than it is to decrease the size of a CCD. Accordingly, CISs are widely used in a variety of application fields, such as digital still cameras or digital video cameras for example.
FIGS. 1A-1E disclose a prior art method for fabricating a CIS. As disclosed in FIG. 1A, a low-concentration P− type epitaxial layer 62 is formed in a high-concentration P++ type semiconductor substrate 61 using an epitaxial process. An active region and a device isolation region are defined in the semiconductor substrate 61. A device isolation film 63 is then formed in the device isolation region using a shallow trench isolation (STI) process. Thereafter, a gate insulating film 64 and a conductive layer, such as a high-concentration polycrystalline silicon layer for example, are sequentially deposited on a whole surface of the epitaxial layer 62 including the device isolation film 63. The conductive layer and the gate insulating film 64 are then selectively removed, thereby forming a gate electrode 65.
As disclosed in FIG. 1B, a first photoresist film 66 is coated above a whole surface of the semiconductor substrate 61 and is patterned to expose each blue, green, and red photodiode region in an exposure and development process. Subsequently, low-concentration N type dopants are implanted in the epitaxial layer 62 with the patterned first photoresist film 66 as a mask, thereby forming an N− type diffusion region 67 that is the blue, green, and red photodiode region. When the N− type diffusion region 67 for the photodiode region is formed, ion implantation of phosphorous (P) is implemented. In order to enhance the efficiency of signal transmission, a series of two processes are performed with different ion implantation energies.
As disclosed in FIG. 1C, the first photoresist film 66 is thoroughly removed. An insulation film is then deposited and etched back above an entire surface of the semiconductor substrate 61. Thus, insulating sidewalls 68 are formed at both side surfaces of the gate electrode 65. After a second photoresist film 69 is coated above an entire surface of the semiconductor substrate 61, it is patterned to cover the photodiode region and expose a source/drain region of each transistor through an exposure and development process. Next, high-concentration N+ type dopants are implanted in the exposed source/drain region using the patterned second photoresist film 69 as a mask, thereby forming an N+ type diffusion region (a floated diffusion region) 70.
As disclosed in FIG. 1D, the second photoresist film 69 is removed. After a third photoresist film 71 is coated above an entire surface of the semiconductor substrate 61, it is patterned to expose each photodiode region by an exposure and development process. P0 type dopants, such as BF2+ for example, are implanted in the photodiode region including the N type diffusion region 67, using the patterned third photoresist film 71 as a mask. Thus, a P0 type diffusion region 72 is formed on the N type diffusion region 62. In this connection, electrons may be generated in a surface of a photodiode due to a defect of the interface between the photodiode and the semiconductor substrate 61. This may cause a movement of the electrons to the photodiode region to thereby generate an undesired signal in the surface. Thus, the P0 type diffusion region 72 with many holes formed at its upper surface serves to remove the electrons by allowing the electrons to couple with the holes. However, a portion of the electrons remains without removing or coupling with holes and thus, causes a dark current thereby deteriorating a product characteristic of the CMOS sensor.
As disclosed in FIG. 1E, the third photoresist film 71 is removed. The semiconductor substrate 61 is heat-treated, thereby promoting diffusion in each impurity diffusion region. As a P type junction layer is formed thicker by P type ion implantation in order to remove a dark current, dark current decreases but a light sensitivity also decreases. Thus, after ion implantation, P type dopants should not be diffused into the photodiode region.
FIG. 2 discloses a relationship between silicon depth and dopant concentration in a photodiode region formed by primary and secondary ion implantation when the prior art CIS of FIGS. 1A-1E is fabricated. As disclosed in FIG. 2, a series of two N type ion implantations are performed at different energy of 160 KeV and 100 KeV, respectively, to form a photodiode region. Low energy ion implantation is performed at an ion implantation angle of between 4 degrees and 10 degrees. High energy ion implantation is performed at an ion implantation angle of zero degrees.
However, in the prior art, there is a limitation in controlling the diffusion of boron (B) having a small mass and fast diffusion. Accordingly, low energy ion implantation makes it difficult to realize a concentration profile in a desired form.
As disclosed in FIG. 3A, electrons that are a cause of a dark current generated in a surface of a photodiode are mostly removed by coupling with many P type holes, but a part of the electrons naturally flows into an N type region whose energy is low. This leads to the generation of an unnecessary signal to thereby produce a noise in images. Also, it is difficult to control the diffusion of P type dopants into the N type region and therefore, a light sensitivity characteristic, in particular, sensitivity to a blue color-based short wavelength light is deteriorated.
In the prior art, as described above, ion implantation of phosphorous (P) or arsenic (As), which are N type dopants, is performed on the photodiode region of the CIS. After that, ion implantation of BF2+, which is a P type dopant, is implemented. A theoretical approach to the diffusion of boron (B) is mainly affected from a Transient Enhanced Diffusion (TED) effect caused by the interstitial between lattices. Accordingly, in the case of low energy, as disclosed in FIG. 3B, it is difficult to control a doping profile (a concentration profile) when a thermal process is performed after ion implantation of boron.